The 1Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM. It is internally configured as
an octal-bank DRAM.
The 1Gb chip is organized as 8Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and CK
falling). All I/Os are synchronized with a single ended DQS or
differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in